verilog HDLBits刷题[多路复用器]“Mux256to1v”---256-to-1 4-bit multiplexer

一、题目Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel0 should select bits in[3:0], sel1 selects bits in[7:4], sel2 selects bits in[11:8], etc.Expected solution length:Around 1–5 lines.Module Declarationmodule top_module( input [1023:0] in, input [7:0] sel, output [3:0] out );二、分析输入为4bit位宽但in有1024bit即取其中连续的4bit为一输入sel0输出in[3:0],sel1,输出in[7:4],...四bit中看最低的一位其他依次加一四、代码实现module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out[3:0]{in[4*sel3],in[4*sel2],in[4*sel1],in[4*sel]}; endmodule 或者 module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out in[4*sel : 4]; endmodule